1. Field
Example embodiments of the following description relate to a scheduling apparatus and method for synchronization between cores in a real-time multi-core system including a large number of cores having a scratchpad memory (SPM).
2. Description of the Related Art
One of the most noticeable trends in the design of microprocessors may be the utilization of multi-core processors. Since the advent of dual-core products, a movement toward the use of multi-core processors has become more prevalent, with the development of many-core processors, which utilize a large number of core processors, arising.
Historically, multi-core architecture came about as chip density of processors has increased. For example, historically the number of on-chip processing resources has increased based on Moore's law.
Conventional multi-core chips can include about 10 cores, however it is expected that hundreds of cores can be included in a single chip in the near future.
Recently, there has been an increased awareness of problems associated with approaching physical limits of processor frequencies. Concerns due to heat generation and power consumption during the use of a computer are also increasing. As a result, the structure of a multi-core processor is emerging as a powerful alternative, and as a possible new standard.
As the use of multi-core architecture is becoming more common, parallel processing is being increasingly performed in personal computers (PCs), as well as in super computers, including clusters, and even in embedded systems.
In a parallel program, synchronization occurs frequently, to coordinate sub-jobs and to terminate a job. Synchronization refers to timing to perform jobs, that is, adjusting time intervals so that cases may occur at the same time, or occur in regular intervals. To achieve an optimal performance, synchronization needs to enable parallel processing to be efficiently performed using costs added for the parallel processing.
In a computer with a structure of a shared memory that shares a memory between cores, a cache coherency system is required to maintain a coherency of data in a cache of each of the cores. However, as the number of processors increase, it is more difficult to form a cache coherency system.
Furthermore, scalability of a computer having a structure with a shared memory is reduced, compared the scalability of a computer having a structure with a distributed memory. Additionally, when a cache is used in a real-time system, it is more difficult to ensure real-time performance.
Accordingly, a multi-core system using a scratchpad memory (SCM), instead of a cache, is recently being utilized more frequently. However, since considerable costs are incurred in the movement of tasks between cores in a system with a local memory, such as an SCM, it is important to minimize the movement of tasks, and to balance loads between cores through efficiently scheduling.